Charged Coupled Devices (CCDs) are well known monolithic semiconductor devices that find wide application in electronic products and components such as cameras, audio and video media players, memory circuits, analog-to-digital converters and the like. A CCD typically consists of a Metal Oxide Semiconductor (MOS) structure in which minority charge carriers are stored in a spatially defined depletion region (also referred to as a “potential well”) beneath a gate. CCDs can thus be thought of as charge storing devices similar to MOS capacitors. In a typical structure several of these devices are arranged closely together in a row such that charge can be transferred from one to the next. A clock circuit provides the drive signals to the gates that are necessary to move the stored charges along the row in such a way that charge moves from one potential well to the next.
The MOS structures are typically formed by depositing a highly conductive layer of polysilicon on top of an insulting layer of silicon dioxide (“oxide”) covering a p-type substrate. In this way a surface channel CCD is formed. By applying a positive voltage to the polysilicon gate (positive with respect to the substrate), an electric field is generated within the structure. Any conducting electrons close to the surface will thus be attracted towards the gate, accumulating at the silicon/oxide interface, while the holes are pushed into the substrate. This forms a storage region or potential well for electrons beneath each gate.
A so called buried layer CCD is created by incorporating a thin n-doped layer of silicon underneath the oxide. The buried layer is fully depleted in normal operation and thus moves the charge storage region even deeper into the substrate and away from the oxide interface.
The extent or depth of each storage region is also determined by the applied gate voltage, which is turned on and off as required to clock the charge along the row. Careful attention must therefore be paid to the voltage levels applied to the gate, since it is these voltage levels that establish the surface potentials of the channels formed beneath the gates. Thus, these voltages control such properties as charge capacity of the channel, linearity, and charge transfer efficiency between wells. Very often, gate bias voltages are generated as a compensated Direct Current (DC) voltage level, to create a bias level that is stable over temperature and supply voltage.
Several attempts have been made in the prior art to compensate bias voltages for variations in operating conditions. For example, U.S. Pat. No. 4,831,257 issued to McClelland, et al., describes a technique for biasing the gate of an MOS transistor to compensate for variations in the applied supply voltage. A feedback circuit compares the supply voltage to a reference voltage and adjusts a bias voltage to compensate for detected changes in the supply voltage.
U.S. Pat. No. 5,140,623 issued to Imai, et al. describes an input bias circuit for a CCD array. This bias circuit uses a voltage inverting amplifier having an output node connected to a floating diffusion region of a CCD device. A comparator then compares this voltage level, as supplied to the diffusion region, against the voltage of an input signal supplied to an input gate electrode and a level generated by a low level signal generator. The potential level of the input signal of the CCD register is then controlled using the result of this comparison.
However, neither of these prior art techniques recognize the importance of considering both the voltage level of the clock signal applied for charge transfer, as well as the threshold bias voltage of the CCD devices, in order to determine an appropriate surface potential of the intermediate devices.